1. Field of the Invention
The present invention relates to a semiconductor memory circuit having an inspection circuit. The circuit according to the present invention is applicable to a programmable read only memory (PROM).
2. Description of the Related Arts
In the production of PROMs, sometimes portions of a polycrystalline silicon isolation layer between adjacent memory cells are defective because of a break or minute dust particles, so that an electrical leakage occurs between the adjacent memory cells. In a PROM circuit having an electrical leakage, a write operation for programming becomes impossible, and thus the PROM circuit in question is a defective product. Accordingly, an inspection must be carried out to detect the existence of a electrical leakage in produced PROMs before supplying the PROMs to users, to exclude faulty products. Therefore, an inspection arrangement is provided in PROMs being produced.
In a prior art, the inspection of the memory cell is carried out by detecting: a leakage current passing through an output terminal; a current distributor in an ON state; a diode of a memory cell; a leakage resistance between memory cells; another diode of the memory cell; another current distributor in an OFF state; and, a LOW level input terminal of a decoder circuit.
But, because of the voltage drop in transistors in an OFF state in the current distributor due to the base/emitter reverse withstanding voltage of these transistors, and the voltage drop in the base bias resistor in the current distributor, the value of the leakage current is extremely small, and therefore, it is probable that the leakage current cannot be detected, or a discrimination of whether or not the current is caused by a leakage cannot be carried out. In such a situation, the desired inspection of the semiconductor memory circuit cannot be carried out precisely and easily.